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R1LV1616H-I Series
Wide Temperature Range Version 16 M SRAM (1-Mword x 16-bit / 2-Mword x 8-bit)
REJ03C0195-0101 Rev.1.01 Nov.18.2004
Description
The R1LV1616H-I Series is 16-Mbit static RAM organized 1-Mword x 16-bit / 2-Mword x 8-bit. R1LV1616H-I Series has realized higher density, higher performance and low power consumption by employing CMOS process technology (6-transistor memory cell). It offers low power standby power dissipation; therefore, it is suitable for battery backup systems. It is packaged in 48-pin plastic TSOPI for high density surface mounting.
Features
* Single 3.0 V supply: 2.7 V to 3.6 V * Fast access time: 45/55 ns (max) * Power dissipation: Active: 9 mW/MHz (typ) Standby: 1.5 W (typ) * Completely static memory. No clock or timing strobe required * Equal access and cycle times * Common data input and output. Three state output * Battery backup operation. 2 chip selection for battery backup * Temperature range: -40 to +85C * Byte function (x8 mode) available by BYTE# & A-1.
Rev.1.01, Nov.18.2004, page 1 of 19
R1LV1616H-I Series
Ordering Information
Type No. R1LV1616HSA-4LI R1LV1616HSA-4SI R1LV1616HSA-5SI Access time 45 ns 45 ns 55 ns Package 48-pin plastic TSOPI (48P3R-B)
Rev.1.01, Nov.18.2004, page 2 of 19
R1LV1616H-I Series
Pin Arrangement
48-pin TSOP A15 A14 A13 A12 A11 A10 A9 A8 A19 NC WE# CS2 NU UB# LB# A18 A17 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 (Top view) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A16 BYTE# VSS I/O15/A-1 I/O7 I/O14 I/O6 I/O13 I/O5 I/O12 I/O4 VCC I/O11 I/O3 I/O10 I/O2 I/O9 I/O1 I/O8 I/O0 OE# VSS CS1# A0
Rev.1.01, Nov.18.2004, page 3 of 19
R1LV1616H-I Series
Pin Description (TSOP)
Pin name A0 to A19 A-1 to A19 I/O0 to I/O15 CS1# (CS1) CS2 WE# (WE) OE# (OE) LB# (LB) UB# (UB) BYTE# (BYTE) VCC VSS NC NU*
1
Function Address input (word mode) Address input (byte mode) Data input/output Chip select 1 Chip select 2 Write enable Output enable Lower byte select Upper byte select Byte enable Power supply Ground No connection Not used (test mode pin)
Note: 1. This pin should be connected to a ground (VSS), or not be connected (open).
Rev.1.01, Nov.18.2004, page 4 of 19
R1LV1616H-I Series
Block Diagram (TSOP)
LSB
A15 A14 A13 A12 A11 A10 A9 A8 A18 A16 A19 A4 A5
V CC V SS
Row decoder
* * * * *
Memory matrix 8,192 x 128 x 16 8,192 x 256 x 8
MSB
I/O0 Input data control I/O15
* *
Column I/O Column decoder
* *
MSBA17 A7A6 A3 A2 A1A0 A-1 LSB
* *
BYTE# CS2 CS1# LB# UB# WE# OE#
Control logic
Rev.1.01, Nov.18.2004, page 5 of 19
R1LV1616H-I Series
Operation Table (TSOP)
Byte mode
CS1# CS2 WE# OE# UB# LB# BYTE# I/O0 to I/O7 H x L L L x L H H H x x H L H x x L x H x x x x x x x x x x L L L L L High-Z High-Z Dout Din High-Z I/O8 to I/O14 I/O15 High-Z High-Z High-Z High-Z High-Z High-Z High-Z A-1 A-1 High-Z Operation Standby Standby Read Write Output disable
Note: H: VIH, L: VIL, x: VIH or VIL
Word mode
CS1# CS2 WE# OE# UB# LB# BYTE# I/O0 to I/O7 H x x L L L L L L L x L x H H H H H H H x x x H H H L L L H x x x L L L x x x H x x H L H L L H L x x x H L L H L L H x H H H H H H H H H H High-Z High-Z High-Z Dout Dout High-Z Din Din High-Z High-Z I/O8 to I/O14 I/O15 High-Z High-Z High-Z Dout High-Z Dout Din High-Z Din High-Z High-Z High-Z High-Z Dout High-Z Dout Din High-Z Din High-Z Operation Standby Standby Standby Read Lower byte read Upper byte read Write Lower byte write Upper byte write Output disable
Note: H: VIH, L: VIL, x: VIH or VIL
Rev.1.01, Nov.18.2004, page 6 of 19
R1LV1616H-I Series
Absolute Maximum Ratings
Parameter Power supply voltage relative to VSS Terminal voltage on any pin relative to VSS Power dissipation Storage temperature range Storage temperature range under bias Symbol VCC VT PT Tstg Tbias Value -0.5 to +4.6 -0.5*1 to VCC + 0.3*2 1.0 -55 to +125 -40 to +85 Unit V V W C C
Notes: 1. VT min: -2.0 V for pulse half-width 10 ns. 2. Maximum voltage is +4.6 V.
DC Operating Conditions
Parameter Supply voltage Symbol VCC VSS Input high voltage Input low voltage Ambient temperature range Note: VIH VIL Ta Min 2.7 0 2.2 -0.3 -40 Typ 3.0 0 Max 3.6 0 Unit V V Note
VCC + 0.3 V 0.6 +85 V C 1
1. VIL min: -2.0 V for pulse half-width 10 ns.
Rev.1.01, Nov.18.2004, page 7 of 19
R1LV1616H-I Series
DC Characteristics
Parameter Input leakage current Output leakage current Symbol Min |ILI| |ILO| Typ Max 1 1 Unit A A Test conditions*2 Vin = VSS to VCC CS1# = VIH or CS2 = VIL or OE# = VIH or WE# = VIL or LB# = UB# = VIH, VI/O = VSS to VCC CS1# = VIL, CS2 = VIH, Others = VIH/ VIL, II/O = 0 mA Min. cycle, duty = 100%, II/O = 0 mA, CS1# = VIL, CS2 = VIH, WE# = VIH, Others = VIH/VIL Min. cycle, duty = 100%, II/O = 0 mA, CS1# = VIL, CS2 = VIH, Others = VIH/VIL Cycle time = 70 ns, duty = 100%, II/O = 0 mA, CS1# = VIL, CS2 = VIH, WE# = VIH, Others = VIH/VIL Address increment scan or decrement scan Cycle time = 70 ns, duty = 100%, II/O = 0 mA, CS1# = VIL, CS2 = VIH, Others = VIH/VIL Address increment scan or decrement scan Cycle time = 1 s, duty = 100%, II/O = 0 mA, CS1# 0.2 V, CS2 VCC - 0.2 V VIH VCC - 0.2 V, VIL 0.2 V CS2 = VIL 0 V Vin (1) 0 V CS2 0.2 V or (2) CS1# VCC - 0.2 V, CS2 VCC - 0.2 V or (3) LB# = UB# VCC - 0.2 V, CS2 VCC - 0.2 V, CS1# 0.2 V Average value IOH = -1 mA IOH = -100 A IOL = 2 mA IOL = 100 A
Operating current Average operating current
ICC
22*1
20 35
mA mA
ICC1 (READ) ICC1
30*1
50
mA
ICC2*3 (READ)
3*1
8
mA
ICC2*3
20*1
30
mA
ICC3
3*1
8
mA
Standby current Standby current -4SI -5SI
ISB ISB1

0.1*1 0.5*
1
0.5 8
mA A
-4LI
ISB1
0.5*1
25
A
Output high voltage
VOH VOH VOL VOL
2.4

0.4 0.2
V V V V
VCC - 0.2
Output low voltage
Rev.1.01, Nov.18.2004, page 8 of 19
R1LV1616H-I Series
Notes: 1. Typical values are at VCC = 3.0 V, Ta = +25C and not guaranteed. 2. BYTE# VCC - 0.2 V or BYTE# 0.2 V 3. ICC2 is the value measured while the valid address is increasing or decreasing by one bit. Word mode: LSB (least significant bit) is A0. Byte mode: LSB (least significant bit) is A-1.
Capacitance
(Ta = +25C, f = 1.0 MHz)
Parameter Input capacitance Input/output capacitance Note: Symbol Cin CI/O Min Typ Max 8 10 Unit pF pF Test conditions Vin = 0 V VI/O = 0 V Note 1 1
1. This parameter is sampled and not 100% tested.
Rev.1.01, Nov.18.2004, page 9 of 19
R1LV1616H-I Series
AC Characteristics
(Ta = -40 to +85C, VCC = 2.7 V to 3.6 V, unless otherwise noted.) Test Conditions * * * * Input pulse levels: VIL = 0.4 V, VIH = 2.4 V Input rise and fall time: 5 ns Input and output timing reference levels: 1.4 V Output load: See figures (Including scope and jig)
1.4 V
RL=500 Dout 50pF
Rev.1.01, Nov.18.2004, page 10 of 19
R1LV1616H-I Series Read Cycle
R1LV1616H-I -4SI, -4LI Parameter Read cycle time Address access time Chip select access time Symbol tRC tAA tACS1 tACS2 Output enable to output valid Output hold from address change LB#, UB# access time Chip select to output in low-Z tOE tOH tBA tCLZ1 tCLZ2 LB#, UB# enable to low-Z Output enable to output in low-Z Chip deselect to output in high-Z tBLZ tOLZ tCHZ1 tCHZ2 LB#, UB# disable to high-Z Output disable to output in high-Z tBHZ tOHZ Min 45 10 10 10 5 5 0 0 0 0 Max 45 45 45 30 45 20 20 15 15 -5SI Min 55 10 10 10 5 5 0 0 0 0 Max 55 55 55 35 55 20 20 20 20 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 2, 3 2, 3 2, 3 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 Notes
Write Cycle
R1LV1616H-I -4SI, -4LI Parameter Write cycle time Address valid to end of write Chip selection to end of write Write pulse width LB#, UB# valid to end of write Address setup time Write recovery time Data to write time overlap Data hold from write time Output active from end of write Output disable to output in high-Z Write to output in high-Z Symbol tWC tAW tCW tWP tBW tAS tWR tDW tDH tOW tOHZ tWHZ Min 45 45 45 35 45 0 0 25 0 5 0 0 Max 15 15 -5SI Min 55 50 50 40 50 0 0 25 0 5 0 0 Max 20 20 Unit ns ns ns ns ns ns ns ns ns ns ns ns 2 1, 2 1, 2 6 7 5 4 Notes
Rev.1.01, Nov.18.2004, page 11 of 19
R1LV1616H-I Series Byte Control
R1LV1616H-I -4SI, -4LI Parameter BYTE# setup time BYTE# recovery time Symbol tBS tBR Min 5 5 Max -5SI Min 5 5 Max Unit ms ms Notes
Notes: 1. tCHZ, tOHZ, tWHZ and tBHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referred to output voltage levels. 2. This parameter is sampled and not 100% tested. 3. At any given temperature and voltage condition, tHZ max is less than tLZ min both for a given device and from device to device. 4. A write occurs during the overlap of a low CS1#, a high CS2, a low WE# and a low LB# or a low UB#. A write begins at the latest transition among CS1# going low, CS2 going high, WE# going low and LB# going low or UB# going low. A write ends at the earliest transition among CS1# going high, CS2 going low, WE# going high and LB# going high or UB# going high. tWP is measured from the beginning of write to the end of write. 5. tCW is measured from the later of CS1# going low or CS2 going high to the end of write. 6. tAS is measured from the address valid to the beginning of write. 7. tWR is measured from the earliest of CS1# or WE# going high or CS2 going low to the end of write cycle.
Rev.1.01, Nov.18.2004, page 12 of 19
R1LV1616H-I Series
Timing Waveform
Read Cycle*1
t RC Address*2 tAA tACS1 CS1# tCLZ1 tCHZ1 Valid address
CS2
tACS2 tCLZ2 tCHZ2 tBHZ tBA
LB#, UB# tBLZ tOE OE# tOLZ Dout*3 High impedance Valid data tOH tOHZ
Notes: 1. BYTE# > VCC - 0.2 V or BYTE# < 0.2 V 2. Word mode: A0 to A19 Byte mode: A-1 to A19 3. Word mode: I/O0 to I/O15 Byte mode: I/O0 to I/O7
Rev.1.01, Nov.18.2004, page 13 of 19
R1LV1616H-I Series Write Cycle (1)*1 (WE# Clock)
tWC Address*2 Valid address tWR
tCW CS1# tCW CS2 tBW LB#, UB# tAW tWP WE# tAS tDW Din*3 tWHZ Valid data
tDH
tOW High impedance
Dout*3
Notes: 1. BYTE# > VCC - 0.2 V or BYTE# < 0.2 V 2. Word mode: A0 to A19 Byte mode: A-1 to A19 3. Word mode: I/O0 to I/O15 Byte mode: I/O0 to I/O7
Rev.1.01, Nov.18.2004, page 14 of 19
R1LV1616H-I Series Write Cycle (2)*1 (CS1#, CS2 Clock, OE# = VIH)
tWC Address*2 tAS CS1# tAS CS2 tBW LB#, UB# tCW Valid address tAW tCW tWR
tWP WE#
tDW Din*3 Valid data
tDH
Dout*3
High impedance
Notes: 1. BYTE# > VCC - 0.2 V or BYTE# < 0.2 V 2. Word mode: A0 to A19 Byte mode: A-1 to A19 3. Word mode: I/O0 to I/O15 Byte mode: I/O0 to I/O7
Rev.1.01, Nov.18.2004, page 15 of 19
R1LV1616H-I Series Write Cycle (3)*1 (LB#, UB# Clock, OE# = VIH)
tWC Address Valid address tAW tCW CS1# tCW CS2 tAS UB# (LB#) tBW LB# (UB#) tBW tWR
tWP WE# tDW Din-UB (Din-LB) Valid data tDW Valid data tDH tDH
Din-LB (Din-UB) Dout Note: 1. BYTE# > VCC - 0.2 V
High impedance
Rev.1.01, Nov.18.2004, page 16 of 19
R1LV1616H-I Series Byte Control (TSOP)
CS2 CS1# tBS tBR
BYTE#
Rev.1.01, Nov.18.2004, page 17 of 19
R1LV1616H-I Series
Low VCC Data Retention Characteristics
(Ta = -40 to +85C)
Parameter VCC for data retention Symbol Min VDR 1.5 Typ Max 3.6 Unit V Test conditions*2, 3 Vin 0 V (1) 0 V CS2 0.2 V or (2) CS2 VCC - 0.2 V, CS1# VCC - 0.2 V or (3) LB# = UB# VCC - 0.2 V, CS2 VCC - 0.2 V, CS1# 0.2 V VCC = 3.0 V, Vin 0 V (1) 0 V CS2 0.2 V or (2) CS2 VCC - 0.2 V, CS1# VCC - 0.2 V or (3) LB# = UB# VCC - 0.2 V, CS2 VCC - 0.2 V, CS1# 0.2 V Average value See retention waveforms
Data retention current
-4SI -5SI
ICCDR
0.5*1
8
A
-4LI
ICCDR
0.5*1
25
A
Chip deselect to data retention time Operation recovery time
tCDR tR
0 5

ns ms
Notes: 1. Typical values are at VCC = 3.0 V, Ta = +25C and not guaranteed. 2. BYTE# VCC - 0.2 V or BYTE# 0.2 V 3. CS2 controls address buffer, WE# buffer, CS1# buffer, OE# buffer, LB#, UB# buffer and Din buffer. If CS2 controls data retention mode, Vin levels (address, WE#, OE#, CS1#, LB#, UB#, I/O) can be in the high impedance state. If CS1# controls data retention mode, CS2 must be CS2 VCC - 0.2 V or 0 V CS2 0.2 V. The other input levels (address, WE#, OE#, LB#, UB#, I/O) can be in the high impedance state.
Rev.1.01, Nov.18.2004, page 18 of 19
R1LV1616H-I Series Low VCC Data Retention Timing Waveform (1) (CS1# Controlled)
t CDR V CC 2.7 V Data retention mode tR
2.2 V V DR CS1# 0V CS1# VCC - 0.2 V
Low VCC Data Retention Timing Waveform (2) (CS2 Controlled)
t CDR V CC 2.7 V CS2 V DR 0.6 V 0V 0 V < CS2 < 0.2 V Data retention mode tR
Low VCC Data Retention Timing Waveform (3) (LB#, UB# Controlled)
t CDR V CC 2.7 V Data retention mode tR
2.2 V V DR LB#, UB# 0V LB#, UB# V CC - 0.2 V
Rev.1.01, Nov.18.2004, page 19 of 19
Revision History
Rev. Date
R1LV1616H-I Series Data Sheet
Contents of Modification Page Description Initial issue Addition of 2-Mword x 8-bit function
1.00 1.01
Apr. 22, 2004 Nov. 18, 2004
Sales Strategic Planning Div.
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